1. Field of the Invention
The present invention relates to a semiconductor chip package and a multichip package equipped with a plurality of the semiconductor chip packages.
This is counterpart of and claims priority to Japanese Patent Application No. 429531/2003 filed on Dec. 25, 2003, which is herein incorporated by reference.
2. Description of the Related Art
There has been known a semiconductor chip stack type package wherein a plurality of semiconductor chips are laminated or stacked on one another in one package in their thickness direction with the aim of carrying out high-density packaging based on multifunctioning of a semiconductor device.
As one example of such a semiconductor chip laminated package, may be mentioned, a stack type multichip package. The stack type multichip package has a configuration wherein a plurality of semiconductor chips are mounted on a substrate in a state of being stacked or laminated thereon in their thickness direction, and electrode pads of the respective semiconductor chips and electrical connecting portions on the substrate are respectively electrically connected by wire bonding.
As such a stack type multichip package, there is known a configuration wherein electrode pads of a certain semiconductor chip are provided as relay electrode pads for relaying to electrode pads of other semiconductor chip in order to electrically connect a semiconductor chip and a substrate spaced away from each other beyond a connectable range by wire bonding (see, for example, a patent document 1).
There is also known a configuration wherein with a view toward improving productivity of a semiconductor chip laminated package, for example, a plurality of semiconductor chips each having the same structure and function are stacked on one another with being shifted stepwise, and exposed electrode pads and leads of the respective semiconductor chips are electrically connected to one another by wire bonding (see, for example, a patent document 2).
Further, there is known a configuration wherein in order to laminate or stack two semiconductor chips different from each other in terms of their outer sizes and positions of bonding pads, a wiring sheet formed with wires on its surface side is interposed between the two semiconductor chips (see, for example, a patent document 3).
Moreover, there is known a configuration wherein the shapes of electrode pads of a semiconductor chip disposed on the lower side near conductor patterns formed on a substrate, of a plurality of laminated semiconductor chips are of rectangular shapes larger than those of normal electrode pads, and these electrode pads are formed along the peripheral edge of the semiconductor chip. Bonding wires electrically connected to their corresponding electrode pads of the semiconductor chip on the upper side and bonding wires connected to their corresponding electrode pads on the substrate side are respectively connected to the electrode pads each formed to such a larger size (see, for example, a patent document 4).
Patent Document 1    Japanese Unexamined Patent Publication No. 2001-196529
Patent Document 2    Japanese Unexamined Patent Publication No. 2001-298150
Patent Document 3    Japanese Unexamined Patent Publication No. 2001-7278
Patent Document 4    Japanese Unexamined Patent Publication No. 2002-110898
However, the conventional stack type multichip package was accompanied by problems to be described below.
In a structure in which a plurality of semiconductor chips are laminated or stacked with being shifted stepwise, for example, the lower side of a semiconductor chip that protrudes in visor form is placed in a state of being not supported by other semiconductor chip.
Therefore, there may be a case in which when wire bonding is effected onto the semiconductor chip that protrudes in visor form, stress is applied to a root or basal portion of such a visored portion because the bending strength of the semiconductor chip is weak, and hence the basal portion of the visored portion of the semiconductor chip breaks.
There may be a case in which since the bending strength of the semiconductor chip is weak, the force of bonding between electrode pads and bumps becomes insufficient upon bonding, thus resulting in deterioration in package reliability.
There may be a case in which since the bending strength of each semiconductor chip is weak upon sealing the semiconductor chips stacked on the substrate with a resin, cracks occur in the semiconductor chips due to stress concentration caused by a filler contained in a sealing or encapsulating material.
Further, when the semiconductor chips and the leads or substrate are respectively directly connected by bonding wires, the bonding wires become long in length.
As a result, the bonding wires are deformed due to flowability of an encapsulating resin or the like for sealing each semiconductor chip, so that so-called flowage of wires occurs. Consequently, there may be cases in which the wires are brought into contact with one another, thus causing malfunctions such as a short, breaking, etc.
Therefore, there has been proposed a method of, in order to avoid such malfunctions developed due to the wire's flow, making wires different in length from one another as viewed in the direction of package's height and three-dimensionally avoiding contact among the wires. Since, however, the thickness of the package increases in such a case, the present method is not fit for thinning of the package.